Computer scientists unveil architecture for embedded single-chip supercomputer
Aug. 27, 2003
AUSTIN, Texas—Dr. Doug Burger and Dr. Stephen Keckler at The University of Texas at Austin have announced the design of an adaptive, high-performance microprocessor that could revolutionize computing. In collaboration with IBM, they are constructing a prototype system based on this architecture.
This new architecture, called TRIPS (the Tera-Op Reliable Intelligently Adaptive Processing System), is designed to provide supercomputer performance on a single chip. The two computer scientists are leading a team funded by the Defense Advanced Research Projects Agency (DARPA) to develop the TRIPS prototype microprocessor and system. The TRIPS architecture will scale in future implementations to deliver more than one trillion operations per second by 2010.
The TRIPS design uses a novel approach called “polymorphism” that permits unprecedented flexibility for running different types of software. The hardware includes a flexible grid of arithmetic circuits that exploits the natural flow of data within a program. The grid can be morphed so that the single piece of hardware can obtain high performance on a wide range of applications. This polymorphism allows TRIPS to support desktop, signal processing, graphics, server, scientific and embedded applications efficiently. This flexibility will allow a single TRIPS chip to be used in many different processor markets, replacing the current approach of having a unique and specialized processor for each market.
The university scientists are working closely with IBM to develop the prototype. Mr. Charles Moore, a senior research fellow at the university and a former chief engineer of IBM’s POWER4 processor, will help with the prototype effort and will lead the effort to commercialize the technology. The team includes researchers at IBM’s Austin Research Lab who are developing long-range technologies necessary for the industrial success of this approach, and engineers at IBM’s World-Wide Design Center, which is expected to be the fabrication partner for the TRIPS processor prototypes.
The prototype will contain up to four processor cores, each capable of executing 16 operations per clock cycle, and a uniquely partitioned cache structure designed to offer higher performance than traditional approaches. The chip will contain more than 250 million transistors and will operate at 500 megahertz. The scientists’ goal is to demonstrate the feasibility of a full-scale industrial development that could offer a 10-gigahertz chip capable of executing more than a trillion instructions per second.
The TRIPS project is supported by a total of $11.1 million in funding from DARPA. The scientists expect to have TRIPS prototype chips and systems running in their laboratory by December 2005.
For more information contact: Barbra Rodriguez, College of Natural Sciences, 512-232-0675, or My Luu, IBM Research, 914-945-2988.